As integrated-circuit technology continues to scale, process variation—the divergence of process parameters from their nominal specifications—is becoming an issue that cannot be ignored at the architecture and system levels. Indeed, variation has major implications, such as increased leakage power consumption in the chips and limited processor frequency improvements [1].
In the context of a Chip Multiprocessor (CMP) system, or components within a CMP system, within-die process variation in current and near-future technologies may cause individual cores in the chip to differ substantially in the amount of power they may consume and in the maximum frequency that they may support. This effect, which has been reported elsewhere [3] suggests that it is no longer accurate to think of large CMP systems as homogeneous systems.